����JFIFXX�����    $.' ",#(7),01444'9=82<.342  2!!22222222222222222222222222222222222222222222222222����"��4�� ���,�PG"Z_�4�˷����kjز�Z�,F+��_z�,�© �����zh6�٨�ic�fu���#ډb���_�N�?��wQ���5-�~�I���8����TK<5o�Iv-�����k�_U_�����~b�M��d����Ӝ�U�Hh��?]��E�w��Q���k�{��_}qFW7HTՑ��Y��F�?_�'ϔ��_�Ջt��=||I ��6�έ"�����D���/[�k�9���Y�8ds|\���Ҿp6�Ҵ���]��.����6�z<�v��@]�i%��$j��~�g��J>��no����pM[me�i$[����s�o�ᘨ�˸ nɜG-�ĨU�ycP�3.DB�li�;��hj���x7Z^�N�h������N3u{�:j�x�힞��#M&��jL P@_���� P��&��o8������9�����@Sz6�t7#O�ߋ �s}Yf�T���lmr����Z)'N��k�۞p����w\�Tȯ?�8`�O��i{wﭹW�[�r�� ��Q4F�׊���3m&L�=��h3����z~��#�\�l :�F,j@�� ʱ�wQT����8�"kJO���6�֚l����}���R�>ډK���]��y����&����p�}b��;N�1�m�r$�|��7�>e�@B�TM*-iH��g�D�)� E�m�|�ؘbҗ�a��Ҿ����t4���o���G��*oCN�rP���Q��@z,|?W[0�����:�n,jWiE��W��$~/�hp\��?��{(�0���+�Y8rΟ�+����>S-S����VN;�}�s?.����� w�9��˟<���Mq4�Wv'��{)0�1mB��V����W[�����8�/<� �%���wT^�5���b��)iM� pg�N�&ݝ��VO~�q���u���9� ����!��J27����$O-���! �:�%H��� ـ����y�ΠM=t{!S�� oK8������t<����è:a������[�����ա�H���~��w��Qz`�po�^ ����Q��n� �,uu�C�$ ^���,������8�#��:�6��e�|~���!�3�3.�\0��q��o�4`.|� ����y�Q�`~;�d�ׯ,��O�Zw�������`73�v�܋�<���Ȏ�� ـ4k��5�K�a�u�=9Yd��$>x�A�&�� j0� ���vF��� Y�|�y��� ~�6�@c��1vOp�Ig����4��l�OD���L����� R���c���j�_�uX6��3?nk��Wy�f;^*B� ��@�~a�`��Eu������+���6�L��.ü>��}y���}_�O�6�͐�:�YrG�X��kG�����l^w���~㒶sy��Iu�!� W ��X��N�7BV��O��!X�2����wvG�R�f�T#�����t�/?���%8�^�W�aT��G�cL�M���I��(J����1~�8�?aT ���]����AS�E��(��*E}� 2��#I/�׍qz��^t�̔���b�Yz4x���t�){ OH��+(E��A&�N�������XT��o��"�XC��'���)}�J�z�p� ��~5�}�^����+�6����w��c��Q�|Lp�d�H��}�(�.|����k��c4^�"�����Z?ȕ ��a<�L�!039C� �Eu�C�F�Ew�ç ;�n?�*o���B�8�bʝ���'#Rqf���M}7����]����s2tcS{�\icTx;�\��7K���P���ʇ Z O-��~��c>"��?�������P��E��O�8��@�8��G��Q�g�a�Վ���󁶠�䧘��_%#r�>�1�z�a��eb��qcPѵ��n���#L��� =��׀t� L�7�`��V���A{�C:�g���e@�w1 Xp3�c3�ġ����p��M"'-�@n4���fG��B3�DJ�8[Jo�ߐ���gK)ƛ��$���� ���8�3�����+���� �����6�ʻ���� ���S�kI�*KZlT _`���?��K����QK�d����B`�s}�>���`��*�>��,*@J�d�oF*����弝��O}�k��s��]��y�ߘ��c1G�V���<=�7��7����6�q�PT��tXԀ�!9*4�4Tހ3XΛex�46���Y��D ����� �BdemDa����\�_l,��G�/���֌7���Y�](�xTt^%�GE�����4�}bT���ڹ�����;Y)���B�Q��u��>J/J �⮶.�XԄ��j�ݳ�+E��d ��r�5�_D�1 ��o�� �B�x�΢�#���<��W�����8���R6�@g�M�.��� dr�D��>(otU��@x=��~v���2� ӣ�d�oBd��3�eO�6�㣷�����ݜ6��6Y��Qz`��S��{���\P�~z m5{J/L��1������<�e�ͅPu�b�]�ϔ���'������f�b� Zpw��c`"��i���BD@:)ִ�:�]��hv�E�w���T�l��P���"Ju�}��وV J��G6��. J/�Qgl߭�e�����@�z�Zev2u�)]կ�����7x���s�M�-<ɯ�c��r�v�����@��$�ޮ}lk���a���'����>x��O\�ZFu>�����ck#��&:��`�$�ai�>2Δ����l���oF[h��lE�ܺ�Πk:)���`�� $[6�����9�����kOw�\|���8}������ބ:��񶐕��I�A1/�=�2[�,�!��.}gN#�u����b��� ~��݊��}34q����d�E��Lc��$��"�[q�U�硬g^��%B �z���r�pJ�ru%v\h1Y�ne`ǥ:g���pQM~�^�Xi� ��`S�:V29.�P���V�?B�k�� AEvw%�_�9C�Q����wKekPؠ�\�;Io d�{ ߞo�c1eP����\� `����E=���@K<�Y���eڼ�J���w����{av�F�'�M�@/J��+9p���|]�����Iw &`��8���&M�hg��[�{��Xj��%��Ӓ�$��(����ʹN���<>�I���RY���K2�NPlL�ɀ)��&e����B+ь����( � �JTx���_?EZ� }@ 6�U���뙢ط�z��dWI�n` D����噥�[��uV��"�G&Ú����2g�}&m��?ċ�"����Om#��������� ��{�ON��"S�X��Ne��ysQ���@Fn��Vg���dX�~nj�]J�<�K]:��FW��b�������62�=��5f����JKw��bf�X�55��~J �%^����:�-�QIE��P��v�nZum� z � ~ə ���� ���ة����;�f��\v���g�8�1��f24;�V���ǔ�)����9���1\��c��v�/'Ƞ�w�������$�4�R-��t���� e�6�/�ġ �̕Ecy�J���u�B���<�W�ַ~�w[B1L۲�-JS΂�{���΃������A��20�c#��@ 0!1@AP"#2Q`$3V�%45a6�FRUq��� ����^7ׅ,$n�������+��F�`��2X'��0vM��p�L=������5��8������u�p~���.�`r�����\���O��,ư�0oS ��_�M�����l���4�kv\JSd���x���SW�<��Ae�IX����������$I���w�:S���y���›R��9�Q[���,�5�;�@]�%���u�@ *ro�lbI �� ��+���%m:�͇ZV�����u�̉����θau<�fc�.����{�4Ա� �Q����*�Sm��8\ujqs]{kN���)qO�y�_*dJ�b�7���yQqI&9�ԌK!�M}�R�;������S�T���1���i[U�ɵz�]��U)V�S6���3$K{�ߊ<�(� E]Զ[ǼENg�����'�\?#)Dkf��J���o��v���'�%ƞ�&K�u�!��b�35LX�Ϸ��63$K�a�;�9>,R��W��3�3� d�JeTYE.Mϧ��-�o�j3+y��y^�c�������VO�9NV\nd�1 ��!͕_)a�v;����թ�M�lWR1��)El��P;��yوÏ�u 3�k�5Pr6<�⒲l�!˞*��u־�n�!�l:����UNW ��%��Chx8vL'��X�@��*��)���̮��ˍ��� ���D-M�+J�U�kvK����+�x8��cY������?�Ԡ��~3mo��|�u@[XeY�C�\Kp�x8�oC�C�&����N�~3-H���� ��MX�s�u<`���~"WL��$8ξ��3���a�)|:@�m�\���^�`�@ҷ)�5p+��6���p�%i)P M���ngc�����#0Aruz���RL+xSS?���ʮ}()#�t��mˇ!��0}}y����<�e� �-ή�Ԩ��X������ MF���ԙ~l L.3���}�V뽺�v�����멬��Nl�)�2����^�Iq��a��M��qG��T�����c3#������3U�Ǎ���}��לS�|qa��ڃ�+���-��2�f����/��bz��ڐ�� �ݼ[2�ç����k�X�2�* �Z�d���J�G����M*9W���s{��w���T��x��y,�in�O�v��]���n����P�$�JB@=4�OTI�n��e�22a\����q�d���%�$��(���:���: /*�K[PR�fr\nڙdN���F�n�$�4�[�� U�zƶ����� �mʋ���,�ao�u 3�z� �x��Kn����\[��VFmbE;�_U��&V�Gg�]L�۪&#n%�$ɯ�dG���D�TI=�%+AB�Ru#��b4�1�»x�cs�YzڙJG��f��Il��d�eF'T� iA��T���uC�$����Y��H?����[!G`}���ͪ� �纤Hv\������j�Ex�K���!���OiƸ�Yj�+u-<���'q����uN�*�r\��+�]���<�wOZ.fp�ێ��,-*)V?j-kÊ#�`�r��dV����(�ݽBk�����G�ƛk�QmUڗe��Z���f}|����8�8��a���i��3'J�����~G_�^���d�8w������ R�`(�~�.��u���l�s+g�bv���W���lGc}��u���afE~1�Ue������Z�0�8�=e�� f@/�jqEKQQ�J��oN��J���W5~M>$6�Lt�;$ʳ{���^��6�{����v6���ķܰg�V�cnn �~z�x�«�,2�u�?cE+Ș�H؎�%�Za�)���X>uW�Tz�Nyo����s���FQƤ��$��*�&�LLXL)�1�" L��eO��ɟ�9=���:t��Z���c��Ž���Y?�ӭV�wv�~,Y��r�ۗ�|�y��GaF�����C�����.�+� ���v1���fήJ�����]�S��T��B��n5sW}y�$��~z�'�c ��8 ��� ,! �p��VN�S��N�N�q��y8z˱�A��4��*��'������2n<�s���^ǧ˭P�Jޮɏ�U�G�L�J�*#��<�V��t7�8����TĜ>��i}K%,���)[��z�21z ?�N�i�n1?T�I�R#��m-�����������������1����lA�`��fT5+��ܐ�c�q՝��ʐ��,���3�f2U�եmab��#ŠdQ�y>\��)�SLY����w#��.���ʑ�f��� ,"+�w�~�N�'�c�O�3F�������N<���)j��&��,-� �љ���֊�_�zS���TǦ����w�>��?�������n��U仆�V���e�����0���$�C�d���rP �m�׈e�Xm�Vu� �L��.�bֹ��� �[Դaզ���*��\y�8�Է:�Ez\�0�Kq�C b��̘��cө���Q��=0Y��s�N��S.���3.���O�o:���#���v7�[#߫ ��5�܎�L���Er4���9n��COWlG�^��0k�%<���ZB���aB_���������'=��{i�v�l�$�uC���mƎҝ{�c㱼�y]���W�i ��ߧc��m�H� m�"�"�����;Y�ߝ�Z�Ǔ�����:S#��|}�y�,/k�Ld� TA�(�AI$+I3��;Y*���Z��}|��ӧO��d�v��..#:n��f>�>���ȶI�TX��� 8��y����"d�R�|�)0���=���n4��6ⲑ�+��r<�O�܂~zh�z����7ܓ�HH�Ga롏���nCo�>������a ���~]���R���̲c?�6(�q�;5%� |�uj�~z8R=X��I�V=�|{v�Gj\gc��q����z�؋%M�ߍ����1y��#��@f^���^�>N�����#x#۹��6�Y~�?�dfPO��{��P�4��V��u1E1J �*|���%���JN��`eWu�zk M6���q t[�� ��g�G���v��WIG��u_ft����5�j�"�Y�:T��ɐ���*�;� e5���4����q$C��2d�}���� _S�L#m�Yp��O�.�C�;��c����Hi#֩%+) �Ӎ��ƲV���SYź��g |���tj��3�8���r|���V��1#;.SQ�A[���S������#���`n�+���$��$I �P\[�@�s��(�ED�z���P��])8�G#��0B��[ى��X�II�q<��9�~[Z멜�Z�⊔IWU&A>�P~�#��dp<�?����7���c��'~���5 ��+$���lx@�M�dm��n<=e�dyX��?{�|Aef ,|n3�<~z�ƃ�uۧ�����P��Y,�ӥQ�*g�#먙R�\���;T��i,��[9Qi歉����c>]9�� ��"�c��P�� �Md?٥��If�ت�u��k��/����F��9�c*9��Ǎ:�ØF���z�n*�@|I�ށ9����N3{'��[�'ͬ�Ҳ4��#}��!�V� Fu��,�,mTIk���v C�7v���B�6k�T9��1�*l� '~��ƞF��lU��'�M ����][ΩũJ_�{�i�I�n��$���L�� j��O�dx�����kza۪��#�E��Cl����x˘�o�����V���ɞ�ljr��)�/,�߬h�L��#��^��L�ф�,íMƁe�̩�NB�L�����iL����q�}��(��q��6IçJ$�W�E$��:������=#����(�K�B����zђ <��K(�N�۫K�w��^O{!����)�H���>x�������lx�?>Պ�+�>�W���,Ly!_�D���Ō�l���Q�!�[ �S����J��1��Ɛ�Y}��b,+�Lo�x�ɓ)����=�y�oh�@�꥟/��I��ѭ=��P�y9��� �ۍYӘ�e+�p�Jnϱ?V\SO%�(�t� ���=?MR�[Ș�����d�/ ��n�l��B�7j� ��!�;ӥ�/�[-���A�>�dN�sLj ��,ɪv��=1c�.SQ�O3�U���ƀ�ܽ�E����������̻��9G�ϷD�7(�}��Ävӌ\�y�_0[w ���<΍>����a_��[0+�L��F.�޺��f�>oN�T����q;���y\��bՃ��y�jH�<|q-eɏ�_?_9+P���Hp$�����[ux�K w�Mw��N�ی'$Y2�=��q���KB��P��~������Yul:�[<����F1�2�O���5=d����]Y�sw:���Ϯ���E��j,_Q��X��z`H1,#II ��d�wr��P˂@�ZJV����y$�\y�{}��^~���[:N����ߌ�U�������O��d�����ؾe��${p>G��3c���Ė�lʌ�� ת��[��`ϱ�-W����dg�I��ig2��� ��}s ��ؤ(%#sS@���~���3�X�nRG�~\jc3�v��ӍL��M[JB�T��s3}��j�Nʖ��W����;7��ç?=X�F=-�=����q�ߚ���#���='�c��7���ڑW�I(O+=:uxq�������������e2�zi+�kuG�R��������0�&e�n���iT^J����~\jy���p'dtG��s����O��3����9* �b#Ɋ�� p������[Bws�T�>d4�ۧs���nv�n���U���_�~,�v����ƜJ1��s�� �QIz��)�(lv8M���U=�;����56��G���s#�K���MP�=��LvyGd��}�VwWBF�'�à �?MH�U�g2�� ����!�p�7Q��j��ڴ����=��j�u��� Jn�A s���uM������e��Ɔ�Ҕ�!)'��8Ϣ�ٔ��ޝ(��Vp���צ֖d=�IC�J�Ǡ{q������kԭ�߸���i��@K����u�|�p=..�*+����x�����z[Aqġ#s2a�Ɗ���RR�)*HRsi�~�a &f��M��P����-K�L@��Z��Xy�'x�{}��Zm+���:�)�) IJ�-i�u���� ���ܒH��'�L(7�y�GӜq���� j��� 6ߌg1�g�o���,kر���tY�?W,���p���e���f�OQS��!K�۟cҒA�|ս�j�>��=⬒��˧L[�� �߿2JaB~R��u�:��Q�] �0H~���]�7��Ƽ�I���(}��cq '�ήET���q�?f�ab���ӥvr� �)o��-Q��_'����ᴎo��K������;��V���o��%���~OK ����*��b�f:���-ťIR��`B�5!RB@���ï�� �u �̯e\�_U�_������� g�ES��3�������QT��a����x����U<~�c?�*�#]�MW,[8O�a�x��]�1bC|踤�P��lw5V%�)�{t�<��d��5���0i�XSU��m:��Z�┵�i�"��1�^B�-��P�hJ��&)O��*�D��c�W��vM��)����}���P��ܗ-q����\mmζZ-l@�}��a��E�6��F�@��&Sg@���ݚ�M����� ȹ 4����#p�\H����dYDo�H���"��\��..R�B�H�z_�/5˘����6��KhJR��P�mƶi�m���3�,#c�co��q�a)*Pt����R�m�k�7x�D�E�\Y�閣_X�<���~�)���c[[�BP����6�Yq���S��0����%_����;��Àv�~�| VS؇ ��'O0��F0��\���U�-�d@�����7�SJ*z��3n��y��P����O���������m�~�P�3|Y��ʉr#�C�<�G~�.,! ���bqx���h~0=��!ǫ�jy����l�O,�[B��~��|9��ٱ����Xly�#�i�B��g%�S��������tˋ���e���ې��\[d�t)��.+u�|1 ������#�~Oj����hS�%��i.�~X���I�H�m��0n���c�1uE�q��cF�RF�o���7� �O�ꮧ� ���ۛ{��ʛi5�rw?׌#Qn�TW��~?y$��m\�\o����%W� ?=>S�N@�� �Ʈ���R����N�)�r"C�:��:����� �����#��qb��Y�. �6[��2K����2u�Ǧ�HYR��Q�MV��� �G�$��Q+.>�����nNH��q�^��� ����q��mM��V��D�+�-�#*�U�̒ ���p욳��u:�������IB���m���PV@O���r[b= �� ��1U�E��_Nm�yKbN�O���U�}�the�`�|6֮P>�\2�P�V���I�D�i�P�O;�9�r�mAHG�W�S]��J*�_�G��+kP�2����Ka�Z���H�'K�x�W�MZ%�O�YD�Rc+o��?�q��Ghm��d�S�oh�\�D�|:W������UA�Qc yT�q������~^�H��/��#p�CZ���T�I�1�ӏT����4��"�ČZ�����}��`w�#�*,ʹ�� ��0�i��課�Om�*�da��^gJ݅{���l�e9uF#T�ֲ��̲�ٞC"�q���ߍ ոޑ�o#�XZTp����@ o�8��(jd��xw�]�,f���`~�|,s��^����f�1���t��|��m�򸄭/ctr��5s��7�9Q�4�H1꠲BB@l9@���C�����+�wp�xu�£Yc�9��?`@#�o�mH�s2��)�=��2�.�l����jg�9$�Y�S�%*L������R�Y������7Z���,*=�䷘$�������arm�o�ϰ���UW.|�r�uf����IGw�t����Zwo��~5 ��YյhO+=8fF�)�W�7�L9lM�̘·Y���֘YLf�큹�pRF���99.A �"wz��=E\Z���'a� 2��Ǚ�#;�'}�G���*��l��^"q��+2FQ� hj��kŦ��${���ޮ-�T�٭cf�|�3#~�RJ����t��$b�(R��(����r���dx� >U b�&9,>���%E\� Ά�e�$��'�q't��*�א���ެ�b��-|d���SB�O�O��$�R+�H�)�܎�K��1m`;�J�2�Y~9��O�g8=vqD`K[�F)k�[���1m޼c��n���]s�k�z$@��)!I �x՝"v��9=�ZA=`Ɠi �:�E��)`7��vI��}d�YI�_ �o�:ob���o ���3Q��&D&�2=�� �Ά��;>�h����y.*ⅥS������Ӭ�+q&����j|UƧ����}���J0��WW< ۋS�)jQR�j���Ư��rN)�Gű�4Ѷ(�S)Ǣ�8��i��W52���No˓� ۍ%�5brOn�L�;�n��\G����=�^U�dI���8$�&���h��'���+�(������cȁ߫k�l��S^���cƗjԌE�ꭔ��gF���Ȓ��@���}O���*;e�v�WV���YJ\�]X'5��ղ�k�F��b 6R�o՜m��i N�i����>J����?��lPm�U��}>_Z&�KK��q�r��I�D�Չ~�q�3fL�:S�e>���E���-G���{L�6p�e,8��������QI��h��a�Xa��U�A'���ʂ���s�+טIjP�-��y�8ۈZ?J$��W�P� ��R�s�]��|�l(�ԓ��sƊi��o(��S0��Y� 8�T97.�����WiL��c�~�dxc�E|�2!�X�K�Ƙਫ਼�$((�6�~|d9u+�qd�^3�89��Y�6L�.I�����?���iI�q���9�)O/뚅����O���X��X�V��ZF[�یgQ�L��K1���RҖr@v�#��X�l��F���Нy�S�8�7�kF!A��sM���^rkp�jP�DyS$N���q��nxҍ!U�f�!eh�i�2�m���`�Y�I�9r�6� �TF���C}/�y�^���Η���5d�'��9A-��J��>{�_l+�`��A���[�'��յ�ϛ#w:݅�%��X�}�&�PSt�Q�"�-��\縵�/����$Ɨh�Xb�*�y��BS����;W�ջ_mc�����vt?2}1�;qS�d�d~u:2k5�2�R�~�z+|HE!)�Ǟl��7`��0�<�,�2*���Hl-��x�^����'_TV�gZA�'j� ^�2Ϊ��N7t�����?w�� �x1��f��Iz�C-Ȗ��K�^q�;���-W�DvT�7��8�Z�������� hK�(P:��Q- �8�n�Z���܃e貾�<�1�YT<�,�����"�6{/ �?�͟��|1�:�#g��W�>$����d��J��d�B��=��jf[��%rE^��il:��B���x���Sּ�1հ��,�=��*�7 fcG��#q� �eh?��2�7�����,�!7x��6�n�LC�4x��},Geǝ�tC.��vS �F�43��zz\��;QYC,6����~;RYS/6���|2���5���v��T��i����������mlv��������&� �nRh^ejR�LG�f���? �ۉҬܦƩ��|��Ȱ����>3����!v��i�ʯ�>�v��オ�X3e���_1z�Kȗ\<������!�8���V��]��?b�k41�Re��T�q��mz��TiOʦ�Z��Xq���L������q"+���2ۨ��8}�&N7XU7Ap�d�X��~�׿��&4e�o�F��� �H����O���č�c�� 懴�6���͉��+)��v;j��ݷ�� �UV�� i��� j���Y9GdÒJ1��詞�����V?h��l����l�cGs�ځ�������y�Ac�����\V3�? �� ܙg�>qH�S,�E�W�[�㺨�uch�⍸�O�}���a��>�q�6�n6����N6�q������N ! 1AQaq�0@����"2BRb�#Pr���3C`��Scst���$4D���%Td�� ?���N����a��3��m���C���w��������xA�m�q�m���m������$����4n淿t'��C"w��zU=D�\R+w�p+Y�T�&�պ@��ƃ��3ޯ?�Aﶂ��aŘ���@-�����Q�=���9D��ռ�ѻ@��M�V��P��܅�G5�f�Y<�u=,EC)�<�Fy'�"�&�չ�X~f��l�KԆV��?�� �W�N����=(� �;���{�r����ٌ�Y���h{�١������jW����P���Tc�����X�K�r��}���w�R��%��?���E��m�� �Y�q|����\lEE4���r���}�lsI�Y������f�$�=�d�yO����p�����yBj8jU�o�/�S��?�U��*������ˍ�0������u�q�m [�?f����a�� )Q�>����6#������� ?����0UQ����,IX���(6ڵ[�DI�MNލ�c&���υ�j\��X�R|,4��� j������T�hA�e��^���d���b<����n�� �즇�=!���3�^�`j�h�ȓr��jẕ�c�,ٞX����-����a�ﶔ���#�$��]w�O��Ӫ�1y%��L�Y<�wg#�ǝ�̗`�x�xa�t�w��»1���o7o5��>�m뭛C���Uƃߜ}�C���y1Xνm�F8�jI���]����H���ۺиE@I�i;r�8ӭ����V�F�Շ| ��&?�3|x�B�MuS�Ge�=Ӕ�#BE5G�����Y!z��_e��q�р/W>|-�Ci߇�t�1ޯќd�R3�u��g�=0 5��[?�#͏��q�cf���H��{ ?u�=?�?ǯ���}Z��z���hmΔ�BFTW�����<�q�(v� ��!��z���iW]*�J�V�z��gX֧A�q�&��/w���u�gYӘa���; �i=����g:��?2�dž6�ى�k�4�>�Pxs����}������G�9��3 ���)gG�R<>r h�$��'nc�h�P��Bj��J�ҧH� -��N1���N��?��~��}-q!=��_2hc�M��l�vY%UE�@|�v����M2�.Y[|y�"Eï��K�ZF,�ɯ?,q�?v�M 80jx�"�;�9vk�����+ ֧�� �ȺU��?�%�vcV��mA�6��Qg^M����A}�3�nl� QRN�l8�kkn�'�����(��M�7m9و�q���%ޟ���*h$Zk"��$�9��: �?U8�Sl��,,|ɒ��xH(ѷ����Gn�/Q�4�P��G�%��Ա8�N��!� �&�7�;���eKM7�4��9R/%����l�c>�x;������>��C�:�����t��h?aKX�bhe�ᜋ^�$�Iհ �hr7%F$�E��Fd���t��5���+�(M6�t����Ü�UU|zW�=a�Ts�Tg������dqP�Q����b'�m���1{|Y����X�N��b �P~��F^F:����k6�"�j!�� �I�r�`��1&�-$�Bevk:y���#yw��I0��x��=D�4��tU���P�ZH��ڠ底taP��6����b>�xa����Q�#� WeF��ŮNj�p�J* mQ�N����*I�-*�ȩ�F�g�3 �5��V�ʊ�ɮ�a��5F���O@{���NX��?����H�]3��1�Ri_u��������ѕ�� ����0��� F��~��:60�p�͈�S��qX#a�5>���`�o&+�<2�D����: �������ڝ�$�nP���*)�N�|y�Ej�F�5ټ�e���ihy�Z �>���k�bH�a�v��h�-#���!�Po=@k̆IEN��@��}Ll?j�O������߭�ʞ���Q|A07x���wt!xf���I2?Z��<ץ�T���cU�j��]��陎Ltl �}5�ϓ��$�,��O�mˊ�;�@O��jE��j(�ا,��LX���LO���Ц�90�O �.����a��nA���7������j4 ��W��_ٓ���zW�jcB������y՗+EM�)d���N�g6�y1_x��p�$Lv:��9�"z��p���ʙ$��^��JԼ*�ϭ����o���=x�Lj�6�J��u82�A�H�3$�ٕ@�=Vv�]�'�qEz�;I˼��)��=��ɯ���x �/�W(V���p�����$ �m�������u�����񶤑Oqˎ�T����r��㠚x�sr�GC��byp�G��1ߠ�w e�8�$⿄����/�M{*}��W�]˷.�CK\�ުx���/$�WPw���r� |i���&�}�{�X� �>��$-��l���?-z���g����lΆ���(F���h�vS*���b���߲ڡn,|)mrH[���a�3�ר�[1��3o_�U�3�TC�$��(�=�)0�kgP���� ��u�^=��4 �WYCҸ:��vQ�ר�X�à��tk�m,�t*��^�,�}D*� �"(�I��9R����>`�`��[~Q]�#af��i6l��8���6�:,s�s�N6�j"�A4���IuQ��6E,�GnH��zS�HO�uk�5$�I�4��ؤ�Q9�@��C����wp�BGv[]�u�Ov���0I4���\��y�����Q�Ѹ��~>Z��8�T��a��q�ޣ;z��a���/��S��I:�ܫ_�|������>=Z����8:�S��U�I�J��"IY���8%b8���H��:�QO�6�;7�I�S��J��ҌAά3��>c���E+&jf$eC+�z�;��V����� �r���ʺ������my�e���aQ�f&��6�ND��.:��NT�vm�<- u���ǝ\MvZY�N�NT��-A�>jr!S��n�O 1�3�Ns�%�3D@���`������ܟ 1�^c<���� �a�ɽ�̲�Xë#�w�|y�cW�=�9I*H8�p�^(4���՗�k��arOcW�tO�\�ƍR��8����'�K���I�Q�����?5�>[�}��yU�ײ -h��=��% q�ThG�2�)���"ו3]�!kB��*p�FDl�A���,�eEi�H�f�Ps�����5�H:�Փ~�H�0Dت�D�I����h�F3�������c��2���E��9�H��5�zԑ�ʚ�i�X�=:m�xg�hd(�v����׊�9iS��O��d@0ڽ���:�p�5�h-��t�&���X�q�ӕ,��ie�|���7A�2���O%P��E��htj��Y1��w�Ѓ!����  ���� ࢽ��My�7�\�a�@�ţ�J �4�Ȼ�F�@o�̒?4�wx��)��]�P��~�����u�����5�����7X ��9��^ܩ�U;Iꭆ 5 �������eK2�7(�{|��Y׎ �V��\"���Z�1� Z�����}��(�Ǝ"�1S���_�vE30>���p;� ΝD��%x�W�?W?v����o�^V�i�d��r[��/&>�~`�9Wh��y�;���R��� ;;ɮT��?����r$�g1�K����A��C��c��K��l:�'��3 c�ﳯ*"t8�~l��)���m��+U,z��`(�>yJ�?����h>��]��v��ЍG*�{`��;y]��I�T� ;c��NU�fo¾h���/$���|NS���1�S�"�H��V���T���4��uhǜ�]�v;���5�͠x��'C\�SBpl���h}�N����� A�Bx���%��ޭ�l��/����T��w�ʽ]D�=����K���ž�r㻠l4�S�O?=�k �M:� ��c�C�a�#ha���)�ѐxc�s���gP�iG��{+���x���Q���I= �� z��ԫ+ �8"�k�ñ�j=|����c ��y��CF��/��*9ж�h{ �?4�o� ��k�m�Q�N�x��;�Y��4膚�a�w?�6�>e]�����Q�r�:����g�,i"�����ԩA�*M�<�G��b�if��l^M��5� �Ҩ�{����6J��ZJ�����P�*�����Y���ݛu�_4�9�I8�7���������,^ToR���m4�H��?�N�S�ѕw��/S��甍�@�9H�S�T��t�ƻ���ʒU��*{Xs�@����f�����֒Li�K{H�w^���������Ϥm�tq���s� ���ք��f:��o~s��g�r��ט� �S�ѱC�e]�x���a��) ���(b-$(�j>�7q�B?ӕ�F��hV25r[7 Y� }L�R��}����*sg+��x�r�2�U=�*'WS��ZDW]�WǞ�<��叓���{�$�9Ou4��y�90-�1�'*D`�c�^o?(�9��u���ݐ��'PI&� f�Jݮ�������:wS����jfP1F:X �H�9dԯ���˝[�_54 �}*;@�ܨ�� ð�yn�T���?�ןd�#���4rG�ͨ��H�1�|-#���Mr�S3��G�3�����)�.᧏3v�z֑��r����$G"�`j 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]bXc���Nu�No��pS���Q_���_�?i�~�x h5d'�(qw52] ��'ޤ�q��o1�R!���`ywy�A4u���h<קy���\[~�4�\ X�Wt/� 6�����n�F�a8��f���z �3$�t(���q��q�x��^�XWeN'p<-v�!�{�(>ӽDP7��ո0�y)�e$ٕv�Ih'Q�EA�m*�H��RI��=:��� ���4牢) �%_iN�ݧ�l]� �Nt���G��H�L��� ɱ�g<���1V�,�J~�ٹ�"K��Q�� 9�HS�9�?@��k����r�;we݁�]I�!{ �@�G�[�"��`���J:�n]�{�cA�E����V��ʆ���#��U9�6����j�#Y�m\��q�e4h�B�7��C�������d<�?J����1g:ٳ���=Y���D�p�ц� ׈ǔ��1�]26؜oS�'��9�V�FVu�P�h�9�xc�oq�X��p�o�5��Ա5$�9W�V(�[Ak�aY錎qf;�'�[�|���b�6�Ck��)��#a#a˙��8���=äh�4��2��C��4tm^ �n'c���]GQ$[Wҿ��i���vN�{Fu ��1�gx��1┷���N�m��{j-,��x�� Ūm�ЧS�[�s���Gna���䑴�� x�p 8<������97�Q���ϴ�v�aϚG��Rt�Һ׈�f^\r��WH�JU�7Z���y)�vg=����n��4�_)y��D'y�6�]�c�5̪�\� �PF�k����&�c;��cq�$~T�7j ���nç]�<�g ":�to�t}�159�<�/�8������m�b�K#g'I'.W�����6��I/��>v��\�MN��g���m�A�yQL�4u�Lj�j9��#44�t��l^�}L����n��R��!��t��±]��r��h6ٍ>�yҏ�N��fU�� ���� Fm@�8}�/u��jb9������he:A�y�ծw��GpΧh�5����l}�3p468��)U��d��c����;Us/�֔�YX�1�O2��uq�s��`hwg�r~�{ R��mhN��؎*q 42�*th��>�#���E����#��Hv�O����q�}�����6�e��\�,Wk�#���X��b>��p}�դ��3���T5��†��6��[��@�P�y*n��|'f�֧>�lư΂�̺����SU�'*�q�p�_S�����M�� '��c�6�����m�� ySʨ;M��r���Ƌ�m�Kxo,���Gm�P��A�G�:��i��w�9�}M(�^�V��$ǒ�ѽ�9���|���� �a����J�SQ�a���r�B;����}���ٻ֢�2�%U���c�#�g���N�a�ݕ�'�v�[�OY'��3L�3�;,p�]@�S��{ls��X�'���c�jw�k'a�.��}�}&�� �dP�*�bK=ɍ!����;3n�gΊU�ߴmt�'*{,=SzfD� A��ko~�G�aoq�_mi}#�m�������P�Xhύ����mxǍ�΂���巿zf��Q���c���|kc�����?���W��Y�$���_Lv����l߶��c���`?����l�j�ݲˏ!V��6����U�Ђ(A���4y)H���p�Z_�x��>���e��R��$�/�`^'3qˏ�-&Q�=?��CFVR �D�fV�9��{�8g�������n�h�(P"��6�[�D���< E�����~0<@�`�G�6����Hг�cc�� �c�K.5��D��d�B���`?�XQ��2��ٿyqo&+�1^� DW�0�ꊩ���G�#��Q�nL3��c���������/��x ��1�1[y�x�პCW��C�c�UĨ80�m�e�4.{�m��u���I=��f�����0QRls9���f���������9���~f�����Ǩ��a�"@�8���ȁ�Q����#c�ic������G��$���G���r/$W�(��W���V�"��m�7�[m�A�m����bo��D� j����۳� l���^�k�h׽����� ��#� iXn�v��eT�k�a�^Y�4�BN��ĕ��0 !01@Q"2AaPq3BR������?���@4�Q�����T3,���㺠�W�[=JK�Ϟ���2�r^7��vc�:�9 �E�ߴ�w�S#d���Ix��u��:��Hp��9E!�� V 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!01"@AQa2Pq#3BR������?��ʩca��en��^��8���<�u#��m*08r��y�N"�<�Ѳ0��@\�p��� �����Kv�D��J8�Fҽ� �f�Y��-m�ybX�NP����}�!*8t(�OqѢ��Q�wW�K��ZD��Δ^e��!� ��B�K��p~�����e*l}z#9ң�k���q#�Ft�o��S�R����-�w�!�S���Ӥß|M�l޶V��!eˈ�8Y���c�ЮM2��tk���� ������J�fS����Ö*i/2�����n]�k�\���|4yX�8��U�P.���Ы[���l��@"�t�<������5�lF���vU�����W��W��;�b�cД^6[#7@vU�xgZv��F�6��Q,K�v��� �+Ъ��n��Ǣ��Ft���8��0��c�@�!�Zq s�v�t�;#](B��-�nῃ~���3g������5�J�%���O������n�kB�ĺ�.r��+���#�N$?�q�/�s�6��p��a����a��J/��M�8��6�ܰ"�*������ɗud"\w���aT(����[��F��U՛����RT�b���n�*��6���O��SJ�.�ij<�v�MT��R\c��5l�sZB>F��<7�;EA��{��E���Ö��1U/�#��d1�a�n.1ě����0�ʾR�h��|�R��Ao�3�m3 ��%�� ���28Q� ��y��φ���H�To�7�lW>����#i`�q���c����a��� �m,B�-j����݋�'mR1Ήt�>��V��p���s�0IbI�C.���1R�ea�����]H�6����������4B>��o��](��$B���m�����a�!=��?�B� K�Ǿ+�Ծ"�n���K��*��+��[T#�{E�J�S����Q�����s�5�:�U�\wĐ�f�3����܆&�)����I���Ԇw��E T�lrTf6Q|R�h:��[K�� �z��c֧�G�C��%\��_�a�84��HcO�bi��ؖV��7H �)*ģK~Xhչ0��4?�0��� �E<���}3���#���u�?�� ��|g�S�6ꊤ�|�I#Hڛ� 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Current File : /usr/lib/modules/5.15.0-1084-aws/build/include/linux/mfd/tps65910.h
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * tps65910.h  --  TI TPS6591x
 *
 * Copyright 2010-2011 Texas Instruments Inc.
 *
 * Author: Graeme Gregory <gg@slimlogic.co.uk>
 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
 * Author: Arnaud Deconinck <a-deconinck@ti.com>
 */

#ifndef __LINUX_MFD_TPS65910_H
#define __LINUX_MFD_TPS65910_H

#include <linux/gpio.h>
#include <linux/regmap.h>

/* TPS chip id list */
#define TPS65910			0
#define TPS65911			1

/* TPS regulator type list */
#define REGULATOR_LDO			0
#define REGULATOR_DCDC			1

/*
 * List of registers for component TPS65910
 *
 */

#define TPS65910_SECONDS				0x0
#define TPS65910_MINUTES				0x1
#define TPS65910_HOURS					0x2
#define TPS65910_DAYS					0x3
#define TPS65910_MONTHS					0x4
#define TPS65910_YEARS					0x5
#define TPS65910_WEEKS					0x6
#define TPS65910_ALARM_SECONDS				0x8
#define TPS65910_ALARM_MINUTES				0x9
#define TPS65910_ALARM_HOURS				0xA
#define TPS65910_ALARM_DAYS				0xB
#define TPS65910_ALARM_MONTHS				0xC
#define TPS65910_ALARM_YEARS				0xD
#define TPS65910_RTC_CTRL				0x10
#define TPS65910_RTC_STATUS				0x11
#define TPS65910_RTC_INTERRUPTS				0x12
#define TPS65910_RTC_COMP_LSB				0x13
#define TPS65910_RTC_COMP_MSB				0x14
#define TPS65910_RTC_RES_PROG				0x15
#define TPS65910_RTC_RESET_STATUS			0x16
#define TPS65910_BCK1					0x17
#define TPS65910_BCK2					0x18
#define TPS65910_BCK3					0x19
#define TPS65910_BCK4					0x1A
#define TPS65910_BCK5					0x1B
#define TPS65910_PUADEN					0x1C
#define TPS65910_REF					0x1D
#define TPS65910_VRTC					0x1E
#define TPS65910_VIO					0x20
#define TPS65910_VDD1					0x21
#define TPS65910_VDD1_OP				0x22
#define TPS65910_VDD1_SR				0x23
#define TPS65910_VDD2					0x24
#define TPS65910_VDD2_OP				0x25
#define TPS65910_VDD2_SR				0x26
#define TPS65910_VDD3					0x27
#define TPS65910_VDIG1					0x30
#define TPS65910_VDIG2					0x31
#define TPS65910_VAUX1					0x32
#define TPS65910_VAUX2					0x33
#define TPS65910_VAUX33					0x34
#define TPS65910_VMMC					0x35
#define TPS65910_VPLL					0x36
#define TPS65910_VDAC					0x37
#define TPS65910_THERM					0x38
#define TPS65910_BBCH					0x39
#define TPS65910_DCDCCTRL				0x3E
#define TPS65910_DEVCTRL				0x3F
#define TPS65910_DEVCTRL2				0x40
#define TPS65910_SLEEP_KEEP_LDO_ON			0x41
#define TPS65910_SLEEP_KEEP_RES_ON			0x42
#define TPS65910_SLEEP_SET_LDO_OFF			0x43
#define TPS65910_SLEEP_SET_RES_OFF			0x44
#define TPS65910_EN1_LDO_ASS				0x45
#define TPS65910_EN1_SMPS_ASS				0x46
#define TPS65910_EN2_LDO_ASS				0x47
#define TPS65910_EN2_SMPS_ASS				0x48
#define TPS65910_EN3_LDO_ASS				0x49
#define TPS65910_SPARE					0x4A
#define TPS65910_INT_STS				0x50
#define TPS65910_INT_MSK				0x51
#define TPS65910_INT_STS2				0x52
#define TPS65910_INT_MSK2				0x53
#define TPS65910_INT_STS3				0x54
#define TPS65910_INT_MSK3				0x55
#define TPS65910_GPIO0					0x60
#define TPS65910_GPIO1					0x61
#define TPS65910_GPIO2					0x62
#define TPS65910_GPIO3					0x63
#define TPS65910_GPIO4					0x64
#define TPS65910_GPIO5					0x65
#define TPS65910_GPIO6					0x66
#define TPS65910_GPIO7					0x67
#define TPS65910_GPIO8					0x68
#define TPS65910_JTAGVERNUM				0x80
#define TPS65910_MAX_REGISTER				0x80

/*
 * List of registers specific to TPS65911
 */
#define TPS65911_VDDCTRL				0x27
#define TPS65911_VDDCTRL_OP				0x28
#define TPS65911_VDDCTRL_SR				0x29
#define TPS65911_LDO1					0x30
#define TPS65911_LDO2					0x31
#define TPS65911_LDO5					0x32
#define TPS65911_LDO8					0x33
#define TPS65911_LDO7					0x34
#define TPS65911_LDO6					0x35
#define TPS65911_LDO4					0x36
#define TPS65911_LDO3					0x37
#define TPS65911_VMBCH					0x6A
#define TPS65911_VMBCH2					0x6B

/*
 * List of register bitfields for component TPS65910
 *
 */

/* RTC_CTRL_REG bitfields */
#define TPS65910_RTC_CTRL_STOP_RTC			0x01 /*0=stop, 1=run */
#define TPS65910_RTC_CTRL_AUTO_COMP			0x04
#define TPS65910_RTC_CTRL_GET_TIME			0x40

/* RTC_STATUS_REG bitfields */
#define TPS65910_RTC_STATUS_ALARM               0x40

/* RTC_INTERRUPTS_REG bitfields */
#define TPS65910_RTC_INTERRUPTS_EVERY           0x03
#define TPS65910_RTC_INTERRUPTS_IT_ALARM        0x08

/*Register BCK1  (0x80) register.RegisterDescription */
#define BCK1_BCKUP_MASK					0xFF
#define BCK1_BCKUP_SHIFT				0


/*Register BCK2  (0x80) register.RegisterDescription */
#define BCK2_BCKUP_MASK					0xFF
#define BCK2_BCKUP_SHIFT				0


/*Register BCK3  (0x80) register.RegisterDescription */
#define BCK3_BCKUP_MASK					0xFF
#define BCK3_BCKUP_SHIFT				0


/*Register BCK4  (0x80) register.RegisterDescription */
#define BCK4_BCKUP_MASK					0xFF
#define BCK4_BCKUP_SHIFT				0


/*Register BCK5  (0x80) register.RegisterDescription */
#define BCK5_BCKUP_MASK					0xFF
#define BCK5_BCKUP_SHIFT				0


/*Register PUADEN  (0x80) register.RegisterDescription */
#define PUADEN_EN3P_MASK				0x80
#define PUADEN_EN3P_SHIFT				7
#define PUADEN_I2CCTLP_MASK				0x40
#define PUADEN_I2CCTLP_SHIFT				6
#define PUADEN_I2CSRP_MASK				0x20
#define PUADEN_I2CSRP_SHIFT				5
#define PUADEN_PWRONP_MASK				0x10
#define PUADEN_PWRONP_SHIFT				4
#define PUADEN_SLEEPP_MASK				0x08
#define PUADEN_SLEEPP_SHIFT				3
#define PUADEN_PWRHOLDP_MASK				0x04
#define PUADEN_PWRHOLDP_SHIFT				2
#define PUADEN_BOOT1P_MASK				0x02
#define PUADEN_BOOT1P_SHIFT				1
#define PUADEN_BOOT0P_MASK				0x01
#define PUADEN_BOOT0P_SHIFT				0


/*Register REF	(0x80) register.RegisterDescription */
#define REF_VMBCH_SEL_MASK				0x0C
#define REF_VMBCH_SEL_SHIFT				2
#define REF_ST_MASK					0x03
#define REF_ST_SHIFT					0


/*Register VRTC  (0x80) register.RegisterDescription */
#define VRTC_VRTC_OFFMASK_MASK				0x08
#define VRTC_VRTC_OFFMASK_SHIFT				3
#define VRTC_ST_MASK					0x03
#define VRTC_ST_SHIFT					0


/*Register VIO	(0x80) register.RegisterDescription */
#define VIO_ILMAX_MASK					0xC0
#define VIO_ILMAX_SHIFT					6
#define VIO_SEL_MASK					0x0C
#define VIO_SEL_SHIFT					2
#define VIO_ST_MASK					0x03
#define VIO_ST_SHIFT					0


/*Register VDD1  (0x80) register.RegisterDescription */
#define VDD1_VGAIN_SEL_MASK				0xC0
#define VDD1_VGAIN_SEL_SHIFT				6
#define VDD1_ILMAX_MASK					0x20
#define VDD1_ILMAX_SHIFT				5
#define VDD1_TSTEP_MASK					0x1C
#define VDD1_TSTEP_SHIFT				2
#define VDD1_ST_MASK					0x03
#define VDD1_ST_SHIFT					0


/*Register VDD1_OP  (0x80) register.RegisterDescription */
#define VDD1_OP_CMD_MASK				0x80
#define VDD1_OP_CMD_SHIFT				7
#define VDD1_OP_SEL_MASK				0x7F
#define VDD1_OP_SEL_SHIFT				0


/*Register VDD1_SR  (0x80) register.RegisterDescription */
#define VDD1_SR_SEL_MASK				0x7F
#define VDD1_SR_SEL_SHIFT				0


/*Register VDD2  (0x80) register.RegisterDescription */
#define VDD2_VGAIN_SEL_MASK				0xC0
#define VDD2_VGAIN_SEL_SHIFT				6
#define VDD2_ILMAX_MASK					0x20
#define VDD2_ILMAX_SHIFT				5
#define VDD2_TSTEP_MASK					0x1C
#define VDD2_TSTEP_SHIFT				2
#define VDD2_ST_MASK					0x03
#define VDD2_ST_SHIFT					0


/*Register VDD2_OP  (0x80) register.RegisterDescription */
#define VDD2_OP_CMD_MASK				0x80
#define VDD2_OP_CMD_SHIFT				7
#define VDD2_OP_SEL_MASK				0x7F
#define VDD2_OP_SEL_SHIFT				0

/*Register VDD2_SR  (0x80) register.RegisterDescription */
#define VDD2_SR_SEL_MASK				0x7F
#define VDD2_SR_SEL_SHIFT				0


/*Registers VDD1, VDD2 voltage values definitions */
#define VDD1_2_NUM_VOLT_FINE				73
#define VDD1_2_NUM_VOLT_COARSE				3
#define VDD1_2_MIN_VOLT					6000
#define VDD1_2_OFFSET					125


/*Register VDD3  (0x80) register.RegisterDescription */
#define VDD3_CKINEN_MASK				0x04
#define VDD3_CKINEN_SHIFT				2
#define VDD3_ST_MASK					0x03
#define VDD3_ST_SHIFT					0
#define VDDCTRL_MIN_VOLT				6000
#define VDDCTRL_OFFSET					125

/*Registers VDIG (0x80) to VDAC register.RegisterDescription */
#define LDO_SEL_MASK					0x0C
#define LDO_SEL_SHIFT					2
#define LDO_ST_MASK					0x03
#define LDO_ST_SHIFT					0
#define LDO_ST_ON_BIT					0x01
#define LDO_ST_MODE_BIT					0x02	


/* Registers LDO1 to LDO8 in tps65910 */
#define LDO1_SEL_MASK					0xFC
#define LDO3_SEL_MASK					0x7C
#define LDO_MIN_VOLT					1000
#define LDO_MAX_VOLT					3300


/*Register VDIG1  (0x80) register.RegisterDescription */
#define VDIG1_SEL_MASK					0x0C
#define VDIG1_SEL_SHIFT					2
#define VDIG1_ST_MASK					0x03
#define VDIG1_ST_SHIFT					0


/*Register VDIG2  (0x80) register.RegisterDescription */
#define VDIG2_SEL_MASK					0x0C
#define VDIG2_SEL_SHIFT					2
#define VDIG2_ST_MASK					0x03
#define VDIG2_ST_SHIFT					0


/*Register VAUX1  (0x80) register.RegisterDescription */
#define VAUX1_SEL_MASK					0x0C
#define VAUX1_SEL_SHIFT					2
#define VAUX1_ST_MASK					0x03
#define VAUX1_ST_SHIFT					0


/*Register VAUX2  (0x80) register.RegisterDescription */
#define VAUX2_SEL_MASK					0x0C
#define VAUX2_SEL_SHIFT					2
#define VAUX2_ST_MASK					0x03
#define VAUX2_ST_SHIFT					0


/*Register VAUX33  (0x80) register.RegisterDescription */
#define VAUX33_SEL_MASK					0x0C
#define VAUX33_SEL_SHIFT				2
#define VAUX33_ST_MASK					0x03
#define VAUX33_ST_SHIFT					0


/*Register VMMC  (0x80) register.RegisterDescription */
#define VMMC_SEL_MASK					0x0C
#define VMMC_SEL_SHIFT					2
#define VMMC_ST_MASK					0x03
#define VMMC_ST_SHIFT					0


/*Register VPLL  (0x80) register.RegisterDescription */
#define VPLL_SEL_MASK					0x0C
#define VPLL_SEL_SHIFT					2
#define VPLL_ST_MASK					0x03
#define VPLL_ST_SHIFT					0


/*Register VDAC  (0x80) register.RegisterDescription */
#define VDAC_SEL_MASK					0x0C
#define VDAC_SEL_SHIFT					2
#define VDAC_ST_MASK					0x03
#define VDAC_ST_SHIFT					0


/*Register THERM  (0x80) register.RegisterDescription */
#define THERM_THERM_HD_MASK				0x20
#define THERM_THERM_HD_SHIFT				5
#define THERM_THERM_TS_MASK				0x10
#define THERM_THERM_TS_SHIFT				4
#define THERM_THERM_HDSEL_MASK				0x0C
#define THERM_THERM_HDSEL_SHIFT				2
#define THERM_RSVD1_MASK				0x02
#define THERM_RSVD1_SHIFT				1
#define THERM_THERM_STATE_MASK				0x01
#define THERM_THERM_STATE_SHIFT				0


/*Register BBCH  (0x80) register.RegisterDescription */
#define BBCH_BBSEL_MASK					0x06
#define BBCH_BBSEL_SHIFT				1


/*Register DCDCCTRL  (0x80) register.RegisterDescription */
#define DCDCCTRL_VDD2_PSKIP_MASK			0x20
#define DCDCCTRL_VDD2_PSKIP_SHIFT			5
#define DCDCCTRL_VDD1_PSKIP_MASK			0x10
#define DCDCCTRL_VDD1_PSKIP_SHIFT			4
#define DCDCCTRL_VIO_PSKIP_MASK				0x08
#define DCDCCTRL_VIO_PSKIP_SHIFT			3
#define DCDCCTRL_DCDCCKEXT_MASK				0x04
#define DCDCCTRL_DCDCCKEXT_SHIFT			2
#define DCDCCTRL_DCDCCKSYNC_MASK			0x03
#define DCDCCTRL_DCDCCKSYNC_SHIFT			0


/*Register DEVCTRL  (0x80) register.RegisterDescription */
#define DEVCTRL_PWR_OFF_MASK				0x80
#define DEVCTRL_PWR_OFF_SHIFT				7
#define DEVCTRL_RTC_PWDN_MASK				0x40
#define DEVCTRL_RTC_PWDN_SHIFT				6
#define DEVCTRL_CK32K_CTRL_MASK				0x20
#define DEVCTRL_CK32K_CTRL_SHIFT			5
#define DEVCTRL_SR_CTL_I2C_SEL_MASK			0x10
#define DEVCTRL_SR_CTL_I2C_SEL_SHIFT			4
#define DEVCTRL_DEV_OFF_RST_MASK			0x08
#define DEVCTRL_DEV_OFF_RST_SHIFT			3
#define DEVCTRL_DEV_ON_MASK				0x04
#define DEVCTRL_DEV_ON_SHIFT				2
#define DEVCTRL_DEV_SLP_MASK				0x02
#define DEVCTRL_DEV_SLP_SHIFT				1
#define DEVCTRL_DEV_OFF_MASK				0x01
#define DEVCTRL_DEV_OFF_SHIFT				0


/*Register DEVCTRL2  (0x80) register.RegisterDescription */
#define DEVCTRL2_TSLOT_LENGTH_MASK			0x30
#define DEVCTRL2_TSLOT_LENGTH_SHIFT			4
#define DEVCTRL2_SLEEPSIG_POL_MASK			0x08
#define DEVCTRL2_SLEEPSIG_POL_SHIFT			3
#define DEVCTRL2_PWON_LP_OFF_MASK			0x04
#define DEVCTRL2_PWON_LP_OFF_SHIFT			2
#define DEVCTRL2_PWON_LP_RST_MASK			0x02
#define DEVCTRL2_PWON_LP_RST_SHIFT			1
#define DEVCTRL2_IT_POL_MASK				0x01
#define DEVCTRL2_IT_POL_SHIFT				0


/*Register SLEEP_KEEP_LDO_ON  (0x80) register.RegisterDescription */
#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK		0x80
#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT		7
#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK		0x40
#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT		6
#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK		0x20
#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT		5
#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK		0x10
#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT		4
#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK		0x08
#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT		3
#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK		0x04
#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT		2
#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK		0x02
#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT		1
#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK		0x01
#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT		0


/*Register SLEEP_KEEP_RES_ON  (0x80) register.RegisterDescription */
#define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK		0x80
#define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT		7
#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK		0x40
#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT	6
#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK		0x20
#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT		5
#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK		0x10
#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT		4
#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK		0x08
#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT		3
#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK		0x04
#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT		2
#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK		0x02
#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT		1
#define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK		0x01
#define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT		0


/*Register SLEEP_SET_LDO_OFF  (0x80) register.RegisterDescription */
#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK		0x80
#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT		7
#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK		0x40
#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT		6
#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK		0x20
#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT		5
#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK		0x10
#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT		4
#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK		0x08
#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT		3
#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK		0x04
#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT		2
#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK		0x02
#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT		1
#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK		0x01
#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT		0


/*Register SLEEP_SET_RES_OFF  (0x80) register.RegisterDescription */
#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK		0x80
#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT		7
#define SLEEP_SET_RES_OFF_RSVD_MASK			0x60
#define SLEEP_SET_RES_OFF_RSVD_SHIFT			5
#define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK		0x10
#define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT		4
#define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK		0x08
#define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT		3
#define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK		0x04
#define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT		2
#define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK		0x02
#define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT		1
#define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK		0x01
#define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT		0


/*Register EN1_LDO_ASS	(0x80) register.RegisterDescription */
#define EN1_LDO_ASS_VDAC_EN1_MASK			0x80
#define EN1_LDO_ASS_VDAC_EN1_SHIFT			7
#define EN1_LDO_ASS_VPLL_EN1_MASK			0x40
#define EN1_LDO_ASS_VPLL_EN1_SHIFT			6
#define EN1_LDO_ASS_VAUX33_EN1_MASK			0x20
#define EN1_LDO_ASS_VAUX33_EN1_SHIFT			5
#define EN1_LDO_ASS_VAUX2_EN1_MASK			0x10
#define EN1_LDO_ASS_VAUX2_EN1_SHIFT			4
#define EN1_LDO_ASS_VAUX1_EN1_MASK			0x08
#define EN1_LDO_ASS_VAUX1_EN1_SHIFT			3
#define EN1_LDO_ASS_VDIG2_EN1_MASK			0x04
#define EN1_LDO_ASS_VDIG2_EN1_SHIFT			2
#define EN1_LDO_ASS_VDIG1_EN1_MASK			0x02
#define EN1_LDO_ASS_VDIG1_EN1_SHIFT			1
#define EN1_LDO_ASS_VMMC_EN1_MASK			0x01
#define EN1_LDO_ASS_VMMC_EN1_SHIFT			0


/*Register EN1_SMPS_ASS  (0x80) register.RegisterDescription */
#define EN1_SMPS_ASS_RSVD_MASK				0xE0
#define EN1_SMPS_ASS_RSVD_SHIFT				5
#define EN1_SMPS_ASS_SPARE_EN1_MASK			0x10
#define EN1_SMPS_ASS_SPARE_EN1_SHIFT			4
#define EN1_SMPS_ASS_VDD3_EN1_MASK			0x08
#define EN1_SMPS_ASS_VDD3_EN1_SHIFT			3
#define EN1_SMPS_ASS_VDD2_EN1_MASK			0x04
#define EN1_SMPS_ASS_VDD2_EN1_SHIFT			2
#define EN1_SMPS_ASS_VDD1_EN1_MASK			0x02
#define EN1_SMPS_ASS_VDD1_EN1_SHIFT			1
#define EN1_SMPS_ASS_VIO_EN1_MASK			0x01
#define EN1_SMPS_ASS_VIO_EN1_SHIFT			0


/*Register EN2_LDO_ASS	(0x80) register.RegisterDescription */
#define EN2_LDO_ASS_VDAC_EN2_MASK			0x80
#define EN2_LDO_ASS_VDAC_EN2_SHIFT			7
#define EN2_LDO_ASS_VPLL_EN2_MASK			0x40
#define EN2_LDO_ASS_VPLL_EN2_SHIFT			6
#define EN2_LDO_ASS_VAUX33_EN2_MASK			0x20
#define EN2_LDO_ASS_VAUX33_EN2_SHIFT			5
#define EN2_LDO_ASS_VAUX2_EN2_MASK			0x10
#define EN2_LDO_ASS_VAUX2_EN2_SHIFT			4
#define EN2_LDO_ASS_VAUX1_EN2_MASK			0x08
#define EN2_LDO_ASS_VAUX1_EN2_SHIFT			3
#define EN2_LDO_ASS_VDIG2_EN2_MASK			0x04
#define EN2_LDO_ASS_VDIG2_EN2_SHIFT			2
#define EN2_LDO_ASS_VDIG1_EN2_MASK			0x02
#define EN2_LDO_ASS_VDIG1_EN2_SHIFT			1
#define EN2_LDO_ASS_VMMC_EN2_MASK			0x01
#define EN2_LDO_ASS_VMMC_EN2_SHIFT			0


/*Register EN2_SMPS_ASS  (0x80) register.RegisterDescription */
#define EN2_SMPS_ASS_RSVD_MASK				0xE0
#define EN2_SMPS_ASS_RSVD_SHIFT				5
#define EN2_SMPS_ASS_SPARE_EN2_MASK			0x10
#define EN2_SMPS_ASS_SPARE_EN2_SHIFT			4
#define EN2_SMPS_ASS_VDD3_EN2_MASK			0x08
#define EN2_SMPS_ASS_VDD3_EN2_SHIFT			3
#define EN2_SMPS_ASS_VDD2_EN2_MASK			0x04
#define EN2_SMPS_ASS_VDD2_EN2_SHIFT			2
#define EN2_SMPS_ASS_VDD1_EN2_MASK			0x02
#define EN2_SMPS_ASS_VDD1_EN2_SHIFT			1
#define EN2_SMPS_ASS_VIO_EN2_MASK			0x01
#define EN2_SMPS_ASS_VIO_EN2_SHIFT			0


/*Register EN3_LDO_ASS	(0x80) register.RegisterDescription */
#define EN3_LDO_ASS_VDAC_EN3_MASK			0x80
#define EN3_LDO_ASS_VDAC_EN3_SHIFT			7
#define EN3_LDO_ASS_VPLL_EN3_MASK			0x40
#define EN3_LDO_ASS_VPLL_EN3_SHIFT			6
#define EN3_LDO_ASS_VAUX33_EN3_MASK			0x20
#define EN3_LDO_ASS_VAUX33_EN3_SHIFT			5
#define EN3_LDO_ASS_VAUX2_EN3_MASK			0x10
#define EN3_LDO_ASS_VAUX2_EN3_SHIFT			4
#define EN3_LDO_ASS_VAUX1_EN3_MASK			0x08
#define EN3_LDO_ASS_VAUX1_EN3_SHIFT			3
#define EN3_LDO_ASS_VDIG2_EN3_MASK			0x04
#define EN3_LDO_ASS_VDIG2_EN3_SHIFT			2
#define EN3_LDO_ASS_VDIG1_EN3_MASK			0x02
#define EN3_LDO_ASS_VDIG1_EN3_SHIFT			1
#define EN3_LDO_ASS_VMMC_EN3_MASK			0x01
#define EN3_LDO_ASS_VMMC_EN3_SHIFT			0


/*Register SPARE  (0x80) register.RegisterDescription */
#define SPARE_SPARE_MASK				0xFF
#define SPARE_SPARE_SHIFT				0

#define TPS65910_INT_STS_RTC_PERIOD_IT_MASK			0x80
#define TPS65910_INT_STS_RTC_PERIOD_IT_SHIFT			7
#define TPS65910_INT_STS_RTC_ALARM_IT_MASK			0x40
#define TPS65910_INT_STS_RTC_ALARM_IT_SHIFT			6
#define TPS65910_INT_STS_HOTDIE_IT_MASK				0x20
#define TPS65910_INT_STS_HOTDIE_IT_SHIFT			5
#define TPS65910_INT_STS_PWRHOLD_F_IT_MASK			0x10
#define TPS65910_INT_STS_PWRHOLD_F_IT_SHIFT			4
#define TPS65910_INT_STS_PWRON_LP_IT_MASK			0x08
#define TPS65910_INT_STS_PWRON_LP_IT_SHIFT			3
#define TPS65910_INT_STS_PWRON_IT_MASK				0x04
#define TPS65910_INT_STS_PWRON_IT_SHIFT				2
#define TPS65910_INT_STS_VMBHI_IT_MASK				0x02
#define TPS65910_INT_STS_VMBHI_IT_SHIFT				1
#define TPS65910_INT_STS_VMBDCH_IT_MASK				0x01
#define TPS65910_INT_STS_VMBDCH_IT_SHIFT			0

#define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK			0x80
#define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_SHIFT		7
#define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK			0x40
#define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_SHIFT			6
#define TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK			0x20
#define TPS65910_INT_MSK_HOTDIE_IT_MSK_SHIFT			5
#define TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK			0x10
#define TPS65910_INT_MSK_PWRHOLD_IT_MSK_SHIFT			4
#define TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK			0x08
#define TPS65910_INT_MSK_PWRON_LP_IT_MSK_SHIFT			3
#define TPS65910_INT_MSK_PWRON_IT_MSK_MASK			0x04
#define TPS65910_INT_MSK_PWRON_IT_MSK_SHIFT			2
#define TPS65910_INT_MSK_VMBHI_IT_MSK_MASK			0x02
#define TPS65910_INT_MSK_VMBHI_IT_MSK_SHIFT			1
#define TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK			0x01
#define TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT			0

#define TPS65910_INT_STS2_GPIO0_F_IT_SHIFT			2
#define TPS65910_INT_STS2_GPIO0_F_IT_MASK			0x02
#define TPS65910_INT_STS2_GPIO0_R_IT_SHIFT			1
#define TPS65910_INT_STS2_GPIO0_R_IT_MASK			0x01

#define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_SHIFT			2
#define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK			0x02
#define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_SHIFT			1
#define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK			0x01

/*Register INT_STS  (0x80) register.RegisterDescription */
#define INT_STS_RTC_PERIOD_IT_MASK			0x80
#define INT_STS_RTC_PERIOD_IT_SHIFT			7
#define INT_STS_RTC_ALARM_IT_MASK			0x40
#define INT_STS_RTC_ALARM_IT_SHIFT			6
#define INT_STS_HOTDIE_IT_MASK				0x20
#define INT_STS_HOTDIE_IT_SHIFT				5
#define INT_STS_PWRHOLD_R_IT_MASK			0x10
#define INT_STS_PWRHOLD_R_IT_SHIFT			4
#define INT_STS_PWRON_LP_IT_MASK			0x08
#define INT_STS_PWRON_LP_IT_SHIFT			3
#define INT_STS_PWRON_IT_MASK				0x04
#define INT_STS_PWRON_IT_SHIFT				2
#define INT_STS_VMBHI_IT_MASK				0x02
#define INT_STS_VMBHI_IT_SHIFT				1
#define INT_STS_PWRHOLD_F_IT_MASK			0x01
#define INT_STS_PWRHOLD_F_IT_SHIFT			0


/*Register INT_MSK  (0x80) register.RegisterDescription */
#define INT_MSK_RTC_PERIOD_IT_MSK_MASK			0x80
#define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT			7
#define INT_MSK_RTC_ALARM_IT_MSK_MASK			0x40
#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT			6
#define INT_MSK_HOTDIE_IT_MSK_MASK			0x20
#define INT_MSK_HOTDIE_IT_MSK_SHIFT			5
#define INT_MSK_PWRHOLD_R_IT_MSK_MASK			0x10
#define INT_MSK_PWRHOLD_R_IT_MSK_SHIFT			4
#define INT_MSK_PWRON_LP_IT_MSK_MASK			0x08
#define INT_MSK_PWRON_LP_IT_MSK_SHIFT			3
#define INT_MSK_PWRON_IT_MSK_MASK			0x04
#define INT_MSK_PWRON_IT_MSK_SHIFT			2
#define INT_MSK_VMBHI_IT_MSK_MASK			0x02
#define INT_MSK_VMBHI_IT_MSK_SHIFT			1
#define INT_MSK_PWRHOLD_F_IT_MSK_MASK			0x01
#define INT_MSK_PWRHOLD_F_IT_MSK_SHIFT			0


/*Register INT_STS2  (0x80) register.RegisterDescription */
#define INT_STS2_GPIO3_F_IT_MASK			0x80
#define INT_STS2_GPIO3_F_IT_SHIFT			7
#define INT_STS2_GPIO3_R_IT_MASK			0x40
#define INT_STS2_GPIO3_R_IT_SHIFT			6
#define INT_STS2_GPIO2_F_IT_MASK			0x20
#define INT_STS2_GPIO2_F_IT_SHIFT			5
#define INT_STS2_GPIO2_R_IT_MASK			0x10
#define INT_STS2_GPIO2_R_IT_SHIFT			4
#define INT_STS2_GPIO1_F_IT_MASK			0x08
#define INT_STS2_GPIO1_F_IT_SHIFT			3
#define INT_STS2_GPIO1_R_IT_MASK			0x04
#define INT_STS2_GPIO1_R_IT_SHIFT			2
#define INT_STS2_GPIO0_F_IT_MASK			0x02
#define INT_STS2_GPIO0_F_IT_SHIFT			1
#define INT_STS2_GPIO0_R_IT_MASK			0x01
#define INT_STS2_GPIO0_R_IT_SHIFT			0


/*Register INT_MSK2  (0x80) register.RegisterDescription */
#define INT_MSK2_GPIO3_F_IT_MSK_MASK			0x80
#define INT_MSK2_GPIO3_F_IT_MSK_SHIFT			7
#define INT_MSK2_GPIO3_R_IT_MSK_MASK			0x40
#define INT_MSK2_GPIO3_R_IT_MSK_SHIFT			6
#define INT_MSK2_GPIO2_F_IT_MSK_MASK			0x20
#define INT_MSK2_GPIO2_F_IT_MSK_SHIFT			5
#define INT_MSK2_GPIO2_R_IT_MSK_MASK			0x10
#define INT_MSK2_GPIO2_R_IT_MSK_SHIFT			4
#define INT_MSK2_GPIO1_F_IT_MSK_MASK			0x08
#define INT_MSK2_GPIO1_F_IT_MSK_SHIFT			3
#define INT_MSK2_GPIO1_R_IT_MSK_MASK			0x04
#define INT_MSK2_GPIO1_R_IT_MSK_SHIFT			2
#define INT_MSK2_GPIO0_F_IT_MSK_MASK			0x02
#define INT_MSK2_GPIO0_F_IT_MSK_SHIFT			1
#define INT_MSK2_GPIO0_R_IT_MSK_MASK			0x01
#define INT_MSK2_GPIO0_R_IT_MSK_SHIFT			0


/*Register INT_STS3  (0x80) register.RegisterDescription */
#define INT_STS3_PWRDN_IT_MASK				0x80
#define INT_STS3_PWRDN_IT_SHIFT				7
#define INT_STS3_VMBCH2_L_IT_MASK			0x40
#define INT_STS3_VMBCH2_L_IT_SHIFT			6
#define INT_STS3_VMBCH2_H_IT_MASK			0x20
#define INT_STS3_VMBCH2_H_IT_SHIFT			5
#define INT_STS3_WTCHDG_IT_MASK				0x10
#define INT_STS3_WTCHDG_IT_SHIFT			4
#define INT_STS3_GPIO5_F_IT_MASK			0x08
#define INT_STS3_GPIO5_F_IT_SHIFT			3
#define INT_STS3_GPIO5_R_IT_MASK			0x04
#define INT_STS3_GPIO5_R_IT_SHIFT			2
#define INT_STS3_GPIO4_F_IT_MASK			0x02
#define INT_STS3_GPIO4_F_IT_SHIFT			1
#define INT_STS3_GPIO4_R_IT_MASK			0x01
#define INT_STS3_GPIO4_R_IT_SHIFT			0


/*Register INT_MSK3  (0x80) register.RegisterDescription */
#define INT_MSK3_PWRDN_IT_MSK_MASK			0x80
#define INT_MSK3_PWRDN_IT_MSK_SHIFT			7
#define INT_MSK3_VMBCH2_L_IT_MSK_MASK			0x40
#define INT_MSK3_VMBCH2_L_IT_MSK_SHIFT			6
#define INT_MSK3_VMBCH2_H_IT_MSK_MASK			0x20
#define INT_MSK3_VMBCH2_H_IT_MSK_SHIFT			5
#define INT_MSK3_WTCHDG_IT_MSK_MASK			0x10
#define INT_MSK3_WTCHDG_IT_MSK_SHIFT			4
#define INT_MSK3_GPIO5_F_IT_MSK_MASK			0x08
#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT			3
#define INT_MSK3_GPIO5_R_IT_MSK_MASK			0x04
#define INT_MSK3_GPIO5_R_IT_MSK_SHIFT			2
#define INT_MSK3_GPIO4_F_IT_MSK_MASK			0x02
#define INT_MSK3_GPIO4_F_IT_MSK_SHIFT			1
#define INT_MSK3_GPIO4_R_IT_MSK_MASK			0x01
#define INT_MSK3_GPIO4_R_IT_MSK_SHIFT			0


/*Register GPIO  (0x80) register.RegisterDescription */
#define GPIO_SLEEP_MASK                         0x80
#define GPIO_SLEEP_SHIFT                        7
#define GPIO_DEB_MASK                           0x10
#define GPIO_DEB_SHIFT                          4
#define GPIO_PUEN_MASK                          0x08
#define GPIO_PUEN_SHIFT                         3
#define GPIO_CFG_MASK                           0x04
#define GPIO_CFG_SHIFT                          2
#define GPIO_STS_MASK                           0x02
#define GPIO_STS_SHIFT                          1
#define GPIO_SET_MASK                           0x01
#define GPIO_SET_SHIFT                          0


/*Register JTAGVERNUM  (0x80) register.RegisterDescription */
#define JTAGVERNUM_VERNUM_MASK				0x0F
#define JTAGVERNUM_VERNUM_SHIFT				0


/* Register VDDCTRL (0x27) bit definitions */
#define VDDCTRL_ST_MASK                                  0x03
#define VDDCTRL_ST_SHIFT                                 0


/*Register VDDCTRL_OP  (0x28) bit definitios */
#define VDDCTRL_OP_CMD_MASK                              0x80
#define VDDCTRL_OP_CMD_SHIFT                             7
#define VDDCTRL_OP_SEL_MASK                              0x7F
#define VDDCTRL_OP_SEL_SHIFT                             0


/*Register VDDCTRL_SR  (0x29) bit definitions */
#define VDDCTRL_SR_SEL_MASK                              0x7F
#define VDDCTRL_SR_SEL_SHIFT                             0


/* IRQ Definitions */
#define TPS65910_IRQ_VBAT_VMBDCH			0
#define TPS65910_IRQ_VBAT_VMHI				1
#define TPS65910_IRQ_PWRON				2
#define TPS65910_IRQ_PWRON_LP				3
#define TPS65910_IRQ_PWRHOLD				4
#define TPS65910_IRQ_HOTDIE				5
#define TPS65910_IRQ_RTC_ALARM				6
#define TPS65910_IRQ_RTC_PERIOD				7
#define TPS65910_IRQ_GPIO_R				8
#define TPS65910_IRQ_GPIO_F				9
#define TPS65910_NUM_IRQ				10

#define TPS65911_IRQ_PWRHOLD_F				0
#define TPS65911_IRQ_VBAT_VMHI				1
#define TPS65911_IRQ_PWRON				2
#define TPS65911_IRQ_PWRON_LP				3
#define TPS65911_IRQ_PWRHOLD_R				4
#define TPS65911_IRQ_HOTDIE				5
#define TPS65911_IRQ_RTC_ALARM				6
#define TPS65911_IRQ_RTC_PERIOD				7
#define TPS65911_IRQ_GPIO0_R				8
#define TPS65911_IRQ_GPIO0_F				9
#define TPS65911_IRQ_GPIO1_R				10
#define TPS65911_IRQ_GPIO1_F				11
#define TPS65911_IRQ_GPIO2_R				12
#define TPS65911_IRQ_GPIO2_F				13
#define TPS65911_IRQ_GPIO3_R				14
#define TPS65911_IRQ_GPIO3_F				15
#define TPS65911_IRQ_GPIO4_R				16
#define TPS65911_IRQ_GPIO4_F				17
#define TPS65911_IRQ_GPIO5_R				18
#define TPS65911_IRQ_GPIO5_F				19
#define TPS65911_IRQ_WTCHDG				20
#define TPS65911_IRQ_VMBCH2_H				21
#define TPS65911_IRQ_VMBCH2_L				22
#define TPS65911_IRQ_PWRDN				23

#define TPS65911_NUM_IRQ				24

/* GPIO Register Definitions */
#define TPS65910_GPIO_DEB				BIT(2)
#define TPS65910_GPIO_PUEN				BIT(3)
#define TPS65910_GPIO_CFG				BIT(2)
#define TPS65910_GPIO_STS				BIT(1)
#define TPS65910_GPIO_SET				BIT(0)

/* Max number of TPS65910/11 GPIOs */
#define TPS65910_NUM_GPIO				6
#define TPS65911_NUM_GPIO				9
#define TPS6591X_MAX_NUM_GPIO				9

/* Regulator Index Definitions */
#define TPS65910_REG_VRTC				0
#define TPS65910_REG_VIO				1
#define TPS65910_REG_VDD1				2
#define TPS65910_REG_VDD2				3
#define TPS65910_REG_VDD3				4
#define TPS65910_REG_VDIG1				5
#define TPS65910_REG_VDIG2				6
#define TPS65910_REG_VPLL				7
#define TPS65910_REG_VDAC				8
#define TPS65910_REG_VAUX1				9
#define TPS65910_REG_VAUX2				10
#define TPS65910_REG_VAUX33				11
#define TPS65910_REG_VMMC				12
#define TPS65910_REG_VBB				13

#define TPS65911_REG_VDDCTRL				4
#define TPS65911_REG_LDO1				5
#define TPS65911_REG_LDO2				6
#define TPS65911_REG_LDO3				7
#define TPS65911_REG_LDO4				8
#define TPS65911_REG_LDO5				9
#define TPS65911_REG_LDO6				10
#define TPS65911_REG_LDO7				11
#define TPS65911_REG_LDO8				12

/* Max number of TPS65910/11 regulators */
#define TPS65910_NUM_REGS				14

/* External sleep controls through EN1/EN2/EN3/SLEEP inputs */
#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1		0x1
#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2		0x2
#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3		0x4
#define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP		0x8

/*
 * Sleep keepon data: Maintains the state in sleep mode
 * @therm_keepon: Keep on the thermal monitoring in sleep state.
 * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state.
 * @i2chs_keepon: Keep on high speed internal clock in sleep state.
 */
struct tps65910_sleep_keepon_data {
	unsigned therm_keepon:1;
	unsigned clkout32k_keepon:1;
	unsigned i2chs_keepon:1;
};

/**
 * struct tps65910_board
 * Board platform data may be used to initialize regulators.
 */

struct tps65910_board {
	int gpio_base;
	int irq;
	int irq_base;
	int vmbch_threshold;
	int vmbch2_threshold;
	bool en_ck32k_xtal;
	bool en_dev_slp;
	bool pm_off;
	struct tps65910_sleep_keepon_data slp_keepon;
	bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
	unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];
	struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
};

/**
 * struct tps65910 - tps65910 sub-driver chip access routines
 */

struct tps65910 {
	struct device *dev;
	struct i2c_client *i2c_client;
	struct regmap *regmap;
	unsigned long id;

	/* Device node parsed board data */
	struct tps65910_board *of_plat_data;

	/* IRQ Handling */
	int chip_irq;
	struct regmap_irq_chip_data *irq_data;
};

struct tps65910_platform_data {
	int irq;
	int irq_base;
};

static inline int tps65910_chip_id(struct tps65910 *tps65910)
{
	return tps65910->id;
}

#endif /*  __LINUX_MFD_TPS65910_H */

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